ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 22

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ST7FLITE39F2M3TR

Manufacturer Part Number
ST7FLITE39F2M3TR
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE39F2M3TR

Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE39F2M3TR
Manufacturer:
ST
0
Part Number:
ST7FLITE39F2M3TR
Manufacturer:
ST
Quantity:
20 000
ST7LITE3xF2
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
Figure 11. Stack Manipulation Example
22/173
1
@ 0180h
@ 01FFh
SP
Subroutine
Stack Higher Address = 01FFh
Stack Lower Address = 0180h
CALL
PCH
PCL
SP
Interrupt
Event
PCH
PCH
PCL
PCL
CC
A
X
SP
PUSH Y
PCH
PCH
PCL
PCL
CC
Y
A
X
SP
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in
– When an interrupt is received, the SP is decre-
– On return from interrupt, the SP is incremented
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
mented and the context is pushed on the stack.
and the context is popped from the stack.
POP Y
PCH
PCH
PCL
PCL
CC
Figure
A
X
11.
SP
IRET
PCH
PCL
SP
or RSP
RET

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