Z8F082AHH020SG2156 Zilog, Z8F082AHH020SG2156 Datasheet - Page 40

• Manufacturer Part Number: Z8F082AHH020SG2156
• Description: IC ENCORE XP MCU FLASH 8K
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F082AHH020SG2156

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: Q5278375

Interrupts
INTRODUCTION
INTERRUPT ENABLE AND DISABLE
INTERRUPT PRIORITY
VECTORED INTERRUPT PROCESSING
UM012811-0904
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation and force the
CPU to start an interrupt service routine (ISR). The interrupt service routine exchanges
data, status information, or control information between the CPU and the interrupting
peripheral. When the service routine finishes, the CPU returns to the previous operation.
The eZ8 CPU supports both vectored-and polled-interrupt handling. Interrupts are gener-
ated from internal peripherals, external devices through the port pins, or software. The
Interrupt Controller prioritizes and handles individual interrupt requests before passing
them on to the eZ8 CPU.
The interrupt sources and trigger conditions are device dependent. Refer to the device-spe-
cific Product Specification to determine available interrupt sources (internal and external),
triggering edge options, and exact programming details.
Interrupts are globally enabled and disabled by executing the Enable Interrupts (EI) and
Disable Interrupts (DI) instructions, respectively. These instructions affect the global
interrupt enable control bit in the Interrupt Controller. Enable or disable the individual
interrupts using control registers in the Interrupt Controller. Refer to the device-specific
Product Specification for information on the Interrupt Controller.
The Interrupt Controller prioritizes all interrupts. Refer to the device-specific Product
Specification for information on the Interrupt Controller.
Each eZ8 CPU interrupt is assigned its own vector. When an interrupt occurs, control
passes to the interrupt service routine pointed to by the interrupt’s vector location in Pro-
gram Memory. The sequence of events for a vectored interrupt is as follows:
User Manual
eZ8 CPU
Interrupts
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