Z8F082AHH020SG2156 Zilog, Z8F082AHH020SG2156 Datasheet - Page 180

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Z8F082AHH020SG2156

Manufacturer Part Number
Z8F082AHH020SG2156
Description
IC ENCORE XP MCU FLASH 8K
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet

Specifications of Z8F082AHH020SG2156

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
Q5278375
SRA
Shift Right Arithmetic
SRA dst
UM012811-0904
Mnemonic
SRA
SRA
Operation
Description
Flags
Attributes
Escaped Mode Addressing
This instruction performs an arithmetic shift to the right by one bit position on the destina-
tion operand. Bit 0 replaces the Carry (C) flag. The value of Bit 7 (the Sign bit) does not
change, but its value shifts into Bit 6.
Using Escaped Mode Addressing, address modes R or IR can specify a Working Register.
If the destination address is prefixed by
example, if Working Register R12 (
destination operand in the opcode. To access Registers with addresses
set the Working Group Pointer, RP[7:4], to
C
Z
S
V
D
H
Destination
R1
@R1
D7 D6 D5 D4 D3 D2 D1 D0
Set if the bit rotated from the least-significant bit position was 1 (that is, Bit 0 was 1).
Set if the result is zero; reset otherwise.
Set if Bit 7 of the result is set; reset otherwise.
Reset to 0.
Unaffected.
Unaffected.
dst
Opcode (Hex)
D0
D1
CH
) is the desired destination operand, use
Operand 1
R1
R1
EH
(1110B), a Working Register is inferred. For
EH
C
or use indirect addressing.
eZ8 CPU Instruction Set Description
Operand 2
E0H
Operand 3
User Manual
to
EFH
ECH
eZ8 CPU
, either
as the
170

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