STM8S103F3U6TR STMicroelectronics, STM8S103F3U6TR Datasheet - Page 13
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STM8S103F3U6TR
Manufacturer Part Number
STM8S103F3U6TR
Description
MCU 8BIT 8KB FLASH 20-UFQFPN
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S103F2P6TR.pdf
(113 pages)
Specifications of STM8S103F3U6TR
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VFQFN, 20-VFQFPN
Processor Series
STM8S10x
Core
STM8
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
For Use With
497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8S103F3U6TR
Manufacturer:
MAXIM
Quantity:
1 400
Company:
Part Number:
STM8S103F3U6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM8S103K3 STM8S103F3 STM8S103F2
4.5
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
•
•
•
•
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
1-16 MHz high-speed external crystal (HSE)
Low density
Flash program
memory
(8 Kbytes)
Data
EEPROM
memory
Figure 2: Flash memory organization
DocID15441 Rev 6
Remains write protected during IAP
Data memory area ( 640 bytes)
Write access possible for IAP
Program memory area
Option bytes
UBC area
MASTER
) coming from different oscillators
Programmable
area from 64
bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
Product overview
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