P80C557E4EFB/01,55 NXP Semiconductors, P80C557E4EFB/01,55 Datasheet - Page 39

• Manufacturer Part Number: P80C557E4EFB/01,55
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,55

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 935263156557; P80C557E4FB; P80C557E4FB

Philips Semiconductors
Table 34. Description of IEN1 bits
If the enable bit is 0, then the interrupt is disabled, if the enable bit is 1, then the interrupt is enabled.
Table 35. Description of IP0 bits
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
SYMBOL
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
PAD
PS1
PS0
PX1
PX0
ET2
PT1
PT0
–
IEN1 (E8H)
IP0 (B8H)
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
BIT
BIT
ET2
Enable T2 overflow interrupt(s)
Enable T2 comparator 2 interrupt
Enable T2 comparator 1 interrupt
Enable T2 comparator 0 interrupt
Enable T2 capture register 3 interrupt
Enable T2 capture register 2 interrupt
Enable T2 capture register 1 interrupt
Enable T2 capture register 0 interrupt
Reserved for future use
ADC interrupt priority level
SIO1 (I
SIO0 (UART) interrupt priority level
Timer 1 interrupt priority level
External interrupt 1/Seconds interrupt priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
–
7
7
2
C) interrupt priority level
ECM2
PAD
6
6
Figure 36. Interrupt enable register (IEN1).
Figure 37. Interrupt priority register (IP0).
ECM1
PS1
5
5
39
ECM0
PS0
4
4
P83C557E4/P80C557E4/P89C557E4
FUNCTION
FUNCTION
ECT3
PT1
3
3
ECT2
PX1
2
2
ECT1
PT0
1
1
Product specification
ECT0
PX0
0
0