P80C557E4EFB/01,55 NXP Semiconductors, P80C557E4EFB/01,55 Datasheet - Page 23

• Manufacturer Part Number: P80C557E4EFB/01,55
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,55

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 935263156557; P80C557E4FB; P80C557E4FB

Philips Semiconductors
Table 14. Description of TCON bits
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
TCON (88H)
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
BIT
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor
vectors to interrupt routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
7
Figure 20. Timer/Counter mode control (TCON) register.
TR1
6
TF0
5
23
TR0
4
P83C557E4/P80C557E4/P89C557E4
FUNCTION
IE1
3
IT1
2
IE0
1
Product specification
IT0
0