LPC3180FEL320,551 NXP Semiconductors, LPC3180FEL320,551 Datasheet - Page 23

• Manufacturer Part Number: LPC3180FEL320,551
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320,551

• Program Memory Type: ROMless
• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C/SPI/UART/USB
• Maximum Clock Frequency: 208 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 2
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, LPC3180-DEV-KIT
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 3-ch x 10-bit
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935281874551; LPC3180FEL320-S; LPC3180FEL320-S

NXP Semiconductors
LPC3180_01_1
Preliminary data sheet
6.21.1 Features
6.22.1 Features
6.21 Real-Time Clock (RTC) and battery RAM
6.22 Pulse width modulators
The RTC runs at 32768 Hz using a very low power oscillator. The RTC counts seconds
and can generate alarm interrupts that can wake up the device from Stop mode. The
RTCCLK can also clock the 397x PLL, the Millisecond Timer, the ADC, the Keyboard
Scanner and the PWMs. The RTC up-counter value represents a number of seconds
elapsed since second 0, which is an application determined time. The RTC counter will
reach maximum value after about 136 years. The RTC down-counter is initiated with all
1’s.
Two 32-bit Match registers are readable and writable by the processor. A match will result
in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be
triggered by a match event, and cause an external power supply to turn on all of the
operating voltages, as a way to startup after power has been removed.
The RTC block is implemented in a separate voltage domain. The block is supplied via a
separate supply pin from a battery or other power source.
The RTC block also contains 32 words (128 B) of very low voltage SRAM. This SRAM is
able to hold its contents down to the minimum RTC operating voltage.
The LPC3180/01 provides two PWMs. They are clocked separately by either the main
peripheral clock or the 32 kHz RTC clock. Both PWMs have a duty cycle programmable in
255 steps.
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Flag to indicate that a watchdog reset has occurred.
Programmable watchdog pulse output on RESOUT_N pin.
Can be used as a standard timer if watchdog is not used.
Pause control to stop counting when core is in debug state.
Measures the passage of time in seconds.
32-bit up and down seconds counters.
Ultra low power design to support battery powered systems.
Dedicated 32 kHz oscillator.
An output pin is included to assist in waking up when the chip has had power removed
to all functions except the RTC.
Two 32-bit match registers with interrupt option.
32 words (128 B) of very low voltage SRAM.
The RTC and battery RAM power have an independent power domain and dedicated
supply pins, which can be powered from a battery or power supply.
Clocked by the main peripheral clock or the 32 kHz RTC clock.
Programmable 4-bit prescaler.
Duty cycle programmable in 255 steps.
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
LPC3180/01
© NXP B.V. 2008. All rights reserved.
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