LPC3180 NXP Semiconductors, LPC3180 Datasheet
LPC3180
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LPC3180 Summary of contents
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... Power optimization in this microcontroller is done through process and technology development (Intrinsic Power), and architectural means (Managed Power). The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0 full-speed interface, seven UARTs, two I (SD) interface, and a 10-bit ADC in addition to many other features. ...
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... RAM allows trace via JTAG. Ordering information Package Name Description [1] LFBGA320 plastic low profile fine-pitch ball grid array package; 320 balls; body 13 Rev. 02 — 15 February 2007 LPC3180 8 key matrix. Version SOT824-1 13 0.9 mm © NXP B.V. 2007. All rights reserved ...
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... CONFIG APB slaves AHB- 2-APB 2 UART PWM FAB slaves AHB- 2-FAB WATCHDOG GPIO TIMER Rev. 02 — 15 February 2007 LPC3180 32 bit wide external memory APB slaves SPI SD 2 CARD ETB REGS SYSTEM KEY INTERRUPT RTC CTRL SCAN CONTROLLER 3 HIGH SPEED ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3180 package Table 2. Pin allocation table Pin Symbol Pin Row A 1 U6_IRRX/ 2 PIO_INP[21] 5 JTAG1_TMS 6 9 VSS 10 13 RTCX_OUT 14 17 VDD28 18 21 VDD12 22 Row B 1 KEY_COL5 2 5 JTAG1_TCK 6 9 U1_RX/PIO_INP[15 VSS_RTCCORE 14 [ VSS_OSC 22 Row C ...
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... ADIN1 23 KEY_ROW1 3 VDD_SDRAM18_02 23 [1] i.c. 3 VSS_SDRAM_02 23 [1] i.c. 3 RAM_D[23]/ 23 PIO_SD[04] PWM_OUT1 3 VDD_SDRAM18_03 23 GPI_08/KEY_COL6/ 3 SPI2_BUSY VDD_SDRAM18_04 23 GPI_09/KEY_COL7 3 RAM_D[13] 23 Rev. 02 — 15 February 2007 LPC3180 Symbol Pin Symbol VDD_RTCCORE12 12 VDD_RTC12 [1] i.c. 16 VSS VSS 20 VSS_CORE_01 VSS_PLL397 24 ADIN0 TEST 4 VSS_IO1828_01 JTAG1_NTRST 8 VSS_CORE_02 VSS 12 ONSW VSS 16 VSS_CORE_03 VSS_PLLHCLK 20 VDD_OSC12 ...
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... SPI2_DATIO 3 RAM_WR_N 23 MS_DIO0 3 VSS_SDRAM_07 23 MS_DIO2 3 RAM_A[10] 23 VDD_CORE12_01 3 VSS 7 VSS_CORE_08 11 [1] i.c. 15 VSS_SDRAM_10 19 VSS_SDRAM_08 23 VSS 3 VDD_CORE12_07 7 Rev. 02 — 15 February 2007 LPC3180 Symbol Pin Symbol GPO_07 4 GPO_06 RAM_D[14] 24 RAM_D[12] VSS_IO28_03 4 GPO_09 RAM_D[11] 24 RAM_D[09] GPO_12 4 GPO_21/U4_TX RAM_D[08] 24 RAM_D[06] VSS_CORE_05 4 GPO_15 RAM_D[05] 24 RAM_D[03] GPIO_00 4 SPI2_DATIN RAM_D[00] ...
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... VDD_CORE12_08 19 RAM_A[07] 23 VSS 3 VSS 7 GPO_19 11 [1] i.c. 15 FLASH_RDY 19 RAM_A[04] 23 [1] i.c. 3 USB_OE_TP_N 7 GPO_20 11 [1] i.c. 15 FLASH_IO[07] 19 RAM_A[00] 23 Rev. 02 — 15 February 2007 LPC3180 Symbol Pin Symbol VDD_IO18_03 12 RESOUT_N [1] i.c. 16 i.c. FLASH_IO[04] 20 RAM_A[01] RAM_A[08] 24 RAM_A[11] VSS 4 VSS VDD_IO18_04 8 USB_I2C_SCL VSS 12 VSS_IO18_03 FLASH_CLE 16 VSS_IO18_01 FLASH_IO[02] 20 FLASH_IO[03] RAM_A[06] 24 ...
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... GPIO_02 — general purpose input/output 02 O KEY_ROW6 — keyboard scan row output 6 I/O GPIO_03 — general purpose input/output 03 O KEY_ROW7 — keyboard scan row output 7 I/O general purpose input/output 04 I/O general purpose input/output 05 Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... I/O serial data for JTAG reset input O JTAG return clock output I JTAG clock input I JTAG data input O JTAG data output I JTAG test mode select input Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... I/O” on page 18 O SDRAM byte write mask outputs O SDRAM row address strobe output O SDRAM write strobe output I system reset input O reset output signal I RTC oscillator input O RTC oscillator output Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... PIO_INP[22] — general purpose input to PIO_INP_STATE register I U7_RX — UART 7 receive data input I PIO_INP[23] — general purpose input to PIO_INP_STATE register O UART 7 transmit data output I USB interrupt from external transceiver Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... VDD_CORE or VDD_COREFXD. I ground for the ADC; this should nominally be the same voltage as VSS, but should be isolated to minimize noise and conversion error Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... HCLK PLL I ground for the USB PLL I ground for the RTC block I ground for the 32 kHz RTC oscillator I ground for the SDRAM controller block internally connected; leave open Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... The VFP also provides format conversions between floating-point and integer word formats. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8/16/32 bit. The LPC3180 provides SRAM. 6.5 Memory map The LPC3180 memory map incorporates several distinct regions, as shown in When an application is running, the CPU interrupt vectors are re-mapped to allow them to reside in on-chip SRAM. ...
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... AHB matrix slave port 5 on-chip memory Fig 3. LPC3180 memory map 6.6 SDRAM memory controller The SDRAM memory controller provides an interface between the system bus and external (off-chip) memory devices. A single chip select is supplied, supporting one group of SDRAM in the same address range. The SDRAM controller supports SDR SDRAM ...
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... AHB bus masters. 6.7 NAND flash controllers The LPC3180 includes two NAND flash controllers, one for multi-level NAND flash devices and one for single-level NAND flash devices. The two NAND flash controllers use the same pins to interface to external NAND flash devices, so only one interface is active at a time. 6.7.1 Multi-Level Cell (MLC) NAND fl ...
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... Maximum 10-bit resolution, resolution can be reduced to any amount down to 3 bits for faster conversion. • Three input channels. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... Uses 32 kHz RTC clock 6.12 USB interface The LPC3180 supports USB in either device, host, or OTG configuration. 6.12.1 USB device controller The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller ...
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... Supports the OTG ATX from NXP (ISP 1301) or any external CEA-2011OTG specification compliant ATX. 6.13 UARTs The LPC3180 contains seven UARTs. Four are standard UARTs, and three are special purpose high-speed UARTs. 6.13.1 Standard UARTs The four standard UARTs are downwards compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock ...
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... Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. 6.15 SPI serial I/O controller The LPC3180 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial interface that is able to interface with a large range of serial peripheral or memory devices (SPI mode compatible slave devices). ...
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... Timer/Counter value when an input signal transitions. A capture event may also generate an interrupt. 6.18.1 Features • 32-bit Timer/Counter with programmable 16-bit prescaler. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface 8 matrix. Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... Can be used as a standard timer if watchdog is not used. • Pause control to stop counting when core is in debug state. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... The RTC and battery RAM power have an independent power domain and dedicated supply pins, which can be powered from a battery or power supply. 6.22 Pulse width modulators The LPC3180 provides two PWMs. They are clocked separately by either the main peripheral clock or the 32 kHz RTC clock. Both PWMs have a duty cycle programmable in 255 steps. ...
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... Clocking and power control Clocking in the LPC3180 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed, some peripherals do this automatically. ...
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... The maximum PLL output frequency that is supported by the CPU is 208 MHz. 6.24.3 Power control and modes The LPC3180 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop mode. ...
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... For data accesses either data or address or both can be traced. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface 24 bits captures the trace information under software debugger Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... Conditions Min [2] [3] [4] [5] [6] in 1.8 V range [6] in 3.0 V range [7] 1.8 V pins [7] 3.0 V pins per supply pin - per ground pin - based on package heat transfer, not device power consumption [8] human body model all pins Rev. 02 — 15 February 2007 LPC3180 Max Unit 0.5 +1.3 V 0.5 +1.95 V 0.5 +3.6 V 0.5 +3.3 V 0.5 +1.95 V 0.5 +3.6 V 0.5 +3.3 V 0.5 +1.95 V ...
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... V < (1. 1.8 V inputs 3.0 V inputs 1.8 V inputs 3.0 V inputs 1.8 V outputs 3.0 V outputs 1.8 V outputs 3.0 V outputs 0 0 Rev. 02 — 15 February 2007 LPC3180 [1] Min Typ Max [2] 1.1 1.2 1.3 [2] 0.9 - 1.3 [3] 0.9 - 1.3 [4] 1.1 1.2 1.3 [5] 1.7 1.8 1.95 [6] 2.7 3 3.3 2.7 3 3.3 [7] 1.7 1.8 1.95 2.7 3 3.3 - ...
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... CPU clock = 208 MHz; all peripherals enabled VDD_CORE12 = 0 CPU a clock = 13 MHz VDD_CORE12 = 0 CPU a clock = stopped internally for the pin. is grounded. DD(3V0) Rev. 02 — 15 February 2007 LPC3180 [1] Min Typ Max Unit - 500 A © NXP B.V. 2007. All rights reserved. ...
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... Parameters are valid over operating temperature range unless otherwise specified. [2] Supplied by an external crystal. LPC3180_2 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface [1] Conditions Min [ Rev. 02 — 15 February 2007 LPC3180 Typ Max Unit 13 20 MHz © NXP B.V. 2007. All rights reserved. ...
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... 13.1 13.1 0.5 11.5 11.5 0.15 12.9 12.9 REFERENCES JEDEC JEITA - - - Rev. 02 — 15 February 2007 detail 0.08 0.1 0.05 EUROPEAN PROJECTION LPC3180 SOT824-1 y ISSUE DATE 03-07-09 © NXP B.V. 2007. All rights reserved ...
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... General Purpose Output Interrupt Request Multiply-Accumulate Memory Management Unit Open Host Controller Interface On-The-Go Phase-Locked Loop Pulse Width Modulator Resistor-Capacitor Single Data Rate Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4 “Limiting values”; updated <tbd> values for V Preliminary data sheet Rev. 02 — 15 February 2007 LPC3180 Change notice Supersedes - LPC3180_1 , and © ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 15 February 2007 LPC3180 © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC3180 All rights reserved. Date of release: 15 February 2007 Document identifier: LPC3180_2 ...