LPC3180FEL320 NXP Semiconductors, LPC3180FEL320 Datasheet - Page 14

• Manufacturer Part Number: LPC3180FEL320
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320

• Core Size: 16/32-Bit
• Oscillator Type: External
• Core Processor: ARM9
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 320-LFBGA
• No. Of I/o's: 55
• Ram Memory Size: 64KB
• Cpu Speed: 208MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 2
• Digital Ic Case Style: LFBGA
• Supply Voltage Range: 1.7V
• Controller Family/series: LPC31xx
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3242

NXP Semiconductors
6. Functional description
LPC3180_2
Preliminary data sheet
6.1 Architectural overview
6.2 Vector Floating Point (VFP) coprocessor
The microcontroller is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed CISCs. This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
A 5-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. At any one point in time, several operations are typically in
progress: subsequent instruction fetch, next instruction decode, instruction execution,
memory access, and write-back. The combination of architectural enhancements gives
the ARM9 about 30 % better performance than an ARM7 running at the same clock rate:
The ARM926EJ-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM926EJ-S processor has two instruction sets:
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
In addition, the ARM9 includes enhanced DSP instructions and multiplier, as well as an
enhanced 32-bit MAC block.
This CPU coprocessor provides full support for single-precision and double-precision add,
subtract, multiply, divide, and multiply-accumulate operations at CPU clock speeds. It is
compliant with the IEEE 754 standard, and enables advanced Motor control and DSP
applications. The VFP has three separate pipelines for floating-point MAC operations,
divide or square root operations, and load/store operations. These pipelines can operate
in parallel and can complete execution out of order. All single-precision instructions,
except divide and square root, take one cycle and double-precision multiply and
multiply-accumulate instructions take two cycles. The VFP also provides format
conversions between floating-point and integer word formats.
1. The standard 32-bit ARM set.
2. A 16-bit Thumb set.
•
•
Approximately 1.3 clocks per instruction (1.9 clocks per instruction for ARM7).
Approximately 1.1 Dhrystone MIPS/MHz (0.9 Dhrystone MIPS/MHz for ARM7).
Rev. 02 — 15 February 2007
16/32-bit ARM microcontroller with external memory interface
LPC3180
© NXP B.V. 2007. All rights reserved.
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