LPC3143FET180,551 NXP Semiconductors, LPC3143FET180,551 Datasheet - Page 47

• Manufacturer Part Number: LPC3143FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3143FET180,551

• Package / Case: 180-TFBGA
• Voltage - Supply (vcc/vdd): 1.1 V ~ 1.3 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 270MHz
• Number Of I /o: 20
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Ram Size: 192K x 8
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, JTAG, UART, USB
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V, 1.8 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

NXP Semiconductors
Table 14.
[1]
[2]
[3]
[4]
[5]
[6]
LPC3141_3143
Preliminary data sheet
Symbol
Internal SRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without
dynamic clock scaling; MMU off
I
P
Internal SRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; with
dynamic clock scaling; MMU off
I
P
DD
DD
12 Mhz oscillator running; PLLs off; SYS_BASE and AHB_APB0_BASE Base domain clocks are enabled, driven by 12 Mhz oscillator;
all peripherals off; SUP4 buffers set to input w/PD; SUP8 and SUP3 buffers set to input w/repeater. Shutting off the 12 Mhz osc will
reduce power to 1.4 mW (requires a RSTIN_N to run again).
Running Linux with 100% load; all peripherals on; instruction and data caches on; MMU on.
Dynamic clock scaling active; hardware will automatically switch the SYSBASE clocks to a slow clock (180 / 64 = 2.81 MHz) during
times of bus inactivity. ARM926 and NAND flash clocks are not scaled for this test.
Running Linux idle at prompt; all peripherals on; instruction and data caches on; MMU on.
Running Dhrystone test (600 k/sec); UART and timers enabled; instruction and data caches on; MMU on.
Running Dhrystone test (121.83 k/sec); UART and timers enabled; instruction and data caches off; MMU off.
Parameter
Supply current
Power dissipation
Supply current
Power dissipation
Power consumption
Conditions
core; VDDI = 1.2 V
all other SUP1 supplies: VDDA12 = 1.2 V;
USB_VDDA12_PL = 1.2 V
VDDE_IOA = 1.8 V
VDDE_IOB = 1.8 V
VDDE_IOC = 3.3 V
ADC10B_VDDA33 = 3.3 V
USB_VDDA33 = 3.3 V
USB_VDDA_DRV = 3.3 V
Total for supply domains SUP1, SUP3, SUP4,
SUP8
core; VDDI = 1.2 V
all other SUP1 supplies: VDDA12 = 1.2 V;
USB_VDDA12_PL = 1.2 V
VDDE_IOA = 1.8 V
VDDE_IOB = 1.8 V
VDDE_IOC = 3.3 V
ADC10B_VDDA33 = 3.3 V
USB_VDDA33 = 3.3 V
USB_VDDA_DRV = 3.3 V
Total for supply domains SUP1, SUP3, SUP4,
SUP8
…continued
[6]
[3][6]
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
LPC3141/3143
Min
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Typ
37.95
2.1
2.25
0
0.79
0.0002
0.89
1.75
63.44
17.8
2.1
2.25
0
0.79
0.0002
0.89
1.75
39.26
© NXP B.V. 2010. All rights reserved.
Max
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