LPC3143FET180,551 NXP Semiconductors, LPC3143FET180,551 Datasheet - Page 24

• Manufacturer Part Number: LPC3143FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3143FET180,551

• Package / Case: 180-TFBGA
• Voltage - Supply (vcc/vdd): 1.1 V ~ 1.3 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 270MHz
• Number Of I /o: 20
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Ram Size: 192K x 8
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, JTAG, UART, USB
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V, 1.8 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.14 APB bridge
This module has the following features:
The APB bridge is a bus bridge between AMBA Advanced High-performance Bus (AHB)
and the ARM Peripheral Bus (APB) interface.
The module supports two different architectures:
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Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix).
Round-Robin priority mechanism for bus arbitration: all masters have the same
priority and get bus access in their natural order.
Four devices on a master port (listed in their natural order for bus arbitration):
– DMA
– ARM926 instruction port
– ARM926 data port
– USB OTG
Devices on a slave port (some ports are shared between multiple devices):
– AHB to APB bridge 0
– AHB to APB bridge 1
– AHB to APB bridge 2
– AHB to APB bridge 3
– AHB to APB bridge 4
– Interrupt controller
– NAND flash controller
– MCI SD/SDIO
– USB 2.0 HS OTG
– 96 kB ISRAM
– 96 kB ISRAM
– 128 kB ROM
– MPMC (Multi-Purpose Memory Controller)
Single-clock architecture, synchronous bridge. The same clock is used at the AHB
side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this
architecture.
Dual-clock architecture, asynchronous bridge. Different clocks are used at the AHB
side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1,
AHB-to-APB2, and AHB-to-APB3 bridges use this architecture.
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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