P89V51RB2BBC,557 NXP Semiconductors, P89V51RB2BBC,557 Datasheet - Page 29

• Manufacturer Part Number: P89V51RB2BBC,557
• Description: IC 80C51 MCU 1024 RAM 44TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RB2BBC,557

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935277723557; P89V51RB2BBC; P89V51RB2BBC

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.4.1 Mode 0
6.4.2 Mode 1
Table 18.
Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See
Bit
2
1
0
Fig 8. Timer/counter 0 or 1 in mode 0 (13-bit counter)
INTn pin
TnGate
Tn pin
osc/6
TRn
TCON - Timer/counter control register (address 88H) bit description
Symbol
IT1
IE0
IT0
Figure
Rev. 05 — 12 November 2009
9.
C/T = 0
C/T = 1
Description
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 0.
control
P89V51RB2/RC2/RD2
Figure 8
8-bit microcontrollers with 80C51 core
(Figure
(5-bits)
TLn
shows mode 0 operation.
7). The GATE bit is in the TMOD
(8-bits)
THn
Figure
overflow
8). There are two
© NXP B.V. 2009. All rights reserved.
TFn
…continued
002aaa519
interrupt
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