AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 575

• Manufacturer Part Number: AT91SAM7X512-AU
• Description: MCU ARM 512K HS FLASH 100-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 62
• Ram Memory Size: 128KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.4
37.4.1
37.4.1.1
37.4.1.2
Figure 37-2. Receive Buffer List
6120H–ATARM–17-Feb-09
Programming Interface
Initialization
Configuration
Receive Buffer List
Receive Buffer Queue Pointer
(MAC Register)
Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done
while the transmit and receive circuits are disabled. See the description of the network control
register and network configuration register earlier in this document.
To change loop-back mode, the following sequence of operations must be followed:
Note:
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed
in another data structure that also resides in main memory. This data structure (receive buffer
queue) is a sequence of descriptor entries as defined in
page
To create the list of buffers:
1. Write to network control register to disable transmit and receive circuits.
2. Write to network control register to change loop-back mode.
3. Write to network control register to re-enable transmit or receive circuits.
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap
4. Write address of receive buffer descriptor entry to EMAC register receive_buffer
5. The receive circuits can then be enabled by writing to the address recognition registers
565. It points to this data structure.
create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of
word 0 set to 0.
bit (bit 1 in word 0 set to 1).
queue pointer.
and then to the network control register.
These writes to network control register cannot be combined in any way.
AT91SAM7X512/256/128 Preliminary
Receive Buffer Descriptor List
(In memory)
“Receive Buffer Descriptor Entry” on
Receive Buffer 1
Receive Buffer 0
Receive Buffer N
(In memory)
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