AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 509

• Manufacturer Part Number: AT91SAM7X512-AU
• Description: MCU ARM 512K HS FLASH 100-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 62
• Ram Memory Size: 128KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6120H–ATARM–17-Feb-09
Figure 36-3. Message Acceptance Procedure
If a mailbox is dedicated to receiving several messages (a family of messages) with different
IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the
ID family. Once a message is received, the application must decode the masked bits in the
CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register
(CAN_MFIDx).
For example, if the following message IDs are handled by the same mailbox:
The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:
If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:
If the application associates a handler for each message ID, it may define an array of pointers to
functions:
When a message is received, the corresponding handler can be invoked using CAN_MFIDx reg-
ister and there is no need to check masked bits:
ID0 101000100100010010000100 0 11 00b
ID1 101000100100010010000100 0 11 01b
ID2 101000100100010010000100 0 11 10b
ID3 101000100100010010000100 0 11 11b
ID4 101000100100010010000100 1 11 00b
ID5 101000100100010010000100 1 11 01b
ID6 101000100100010010000100 1 11 10b
ID7 101000100100010010000100 1 11 11b
CAN_MIDx = 001 101000100100010010000100 x 11 xxb
CAN_MAMx = 001 111111111111111111111111 0 11 00b
CAN_MIDx = 001 101000100100010010000100 1 11 10b
CAN_MFIDx = 00000000000000000000000000000110b
void (*pHandler[8])(void);
unsigned int MFID0_register;
MFID0_register = Get_CAN_MFID0_Register();
// Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register
pHandler[MFID0_register]();
CAN_MFIDx
CAN_MIDx
AT91SAM7X512/256/128 Preliminary
Message Accepted
&
CAN_MAMx
==
Yes
No
&
Message Received
Message Refused
509