DSPIC30F6014-20E/PF Microchip Technology, DSPIC30F6014-20E/PF Datasheet - Page 8
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DSPIC30F6014-20E/PF
Manufacturer Part Number
DSPIC30F6014-20E/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6014-20IPF.pdf
(228 pages)
3.DSPIC30F6014-20IPF.pdf
(22 pages)
4.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6014-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601420EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6014-20E/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6011/6012/6013/6014
14. Module: 12-bit 100 ksps ADC
DS80198J-page 8
Input channel scanning allows the ADC to acquire
and convert signals on a selected set of “MUX A”
input pins in sequence. This function is controlled
by the CSCNA (ADCON2<10>) bit and the
ADCSSL SFR.
The ALTS (ADCON2<0>) bit, when set, allows the
ADC to alternately acquire and convert a “MUX A”
input signal and a “MUX B” input signal in an
interleaved fashion.
When both CSCNA and ALTS are set, the ADC
module should scan MUX A input pins while
alternating with a fixed MUX B input pin. However,
for this release of silicon, when both features are
enabled simultaneously, the last input pin enabled
for channel scanning in the ADCSSL SFR is not
scanned. Thus, the ADC converts one channel
less than the number specified in the scan
sequence. Note that this erratum does not affect
devices that have a 10-bit 500 ksps ADC.
Work around
The user may enable an extra (“dummy”) input pin
in the channel-scanning sequence. For example, if
it is desirable to scan pins AN3, AN4 and AN5 on
the set of MUX A inputs while interleaving
conversion from AN6 on the MUX B input, the user
may configure the ADC as follows:
For the configuration above, AN15 is the dummy
input that will not be scanned. On the A/D interrupt,
the A/D buffer will contain conversions from the
following pins in sequence:
- ADCON2 = 0x041D
- ADCHS = 0x0600
- ADCSSL = 0x8038
- ADCBUF0 = AN3
- ADCBUF1 = AN6
- ADCBUF2 = AN4
- ADCBUF3 = AN6
- ADCBUF4 = AN5
- ADCBUF5 = AN6
- ADCBUF6 = AN3
- ADCBUF7 = AN6
15. Module: Data Converter Interface – Slave
The Data Converter Interface (DCI) module does
not function correctly in Slave mode when the
following conditions are true:
• The DCI module is configured to
• The frame length chosen is longer than 1 word,
Work around
The following work around may be applied to
enable DCI communication in Slave mode when it
is configured to transmit one serial clock after the
frame synchronization pulse is received in a
multi-word frame:
1. Set the DJST bit to ‘1’.
2. Enable an additional time slot immediately
3. Enable an additional transmit/receive buffer
4. Shift the data word by 1-bit to the right and load
This work around is now demonstrated by an
example.
Assume, the application needs the DCI module to
act as a Slave transmitting 1 serial clock after the
frame synchronization pulse is received. Further,
assume that the application needs to transmit
16-bit data word on Time Slot 0 and the
communication is over a 256*F
to reduce interrupt frequency, we enable all 4
transmit buffers. The DCI module SFRs should be
initialized as follows before being enabled:
An example of loading the DCI transmit buffers for
the configuration above is shown in Example 11. A
timing diagram in Figure 1 illustrates the various
signals for this example. A similar rule may be
applied to reading the received data from the
RXBUFn SFRs.
transmit/receive one serial clock (bit clock) after
the frame synchronization pulse, DJST
(DCICON1<5>) = 0.
COFSG<3:0> (DCICON2<8:5>) > ‘0000’.
- DCICON1 = 0x0720, DCICON2 = 0x0DEF
following
communication.
word (modify COFSG bits) or an additional bit
per word (modify WS) for each time slot
intended for communication.
the transmit buffer word(s), such that the Least
Significant bit (LSb) of the original data word to
be transmitted is loaded into the additionally
enabled bit of the Transmit Buffer register,
TXBUFn, or the Most Significant bit (MSb) of
the additionally enabled transmit buffer,
TXBUFn + 1.
DCICON3 = 0x0000,
TSCON = RSCON = 0x0003
Mode
each
© 2008 Microchip Technology Inc.
time
slot
S
channel. In order
intended
for