DSPIC30F6014-20E/PF Microchip Technology, DSPIC30F6014-20E/PF Datasheet - Page 12
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DSPIC30F6014-20E/PF
Manufacturer Part Number
DSPIC30F6014-20E/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6014-20IPF.pdf
(228 pages)
3.DSPIC30F6014-20IPF.pdf
(22 pages)
4.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6014-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601420EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6014-20E/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6011/6012/6013/6014
22. Module: Interrupt Controller – Sequential
EXAMPLE 13:
EXAMPLE 14:
DS80198J-page 12
.include
...
DISI
BCLR
...
// note: macro defined in p30f6014.h
#define SET_CPU_IPL (ipl){
#include “p30f6014.h”
. . .
SET_CPU_IPL (3)
. . .
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
int DISI_save;
DISI_save = DISICNT;
asm volatile (“disi #0x3FFF”);\
SRbits.IPL = ipl;
DISICNT = DISI_save; } (void) 0;
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
#2
IEC1, #INT1IE
Interrupts
“p30fxxxx.inc”
USING DISI
USING SET_CPU_IPL MACRO
; protect the disable of INT1
; disable interrupt 1
; next instruction protected by DISI
\
\
\
\
\
Work arounds
Work around 1: For Assembly Language
Source Code
The user may disable interrupt nesting, disable
interrupts before modifying the Interrupt 1 setting
or execute a DISI instruction before modifying the
CPU IPL or Interrupt 1. A minimum DISI value of
2 is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 13. It is necessary to have
DISI active for the cycle after the CPU IPL or
Interrupt 1 is modified.
Work around 2: For C Language Source Code
For applications using C language, MPLAB C30
versions 1.32 and higher provide several macros
for modifying the CPU IPL. The SET_CPU_IPL
macro provides the ability to safely modify the
CPU IPL, as shown in Example 14. There is one
level of DISI, so this macro saves and restores
the DISI state. For temporarily modifying and
restoring
SET_AND_SAVE_CPU_IPL
RESTORE_CPU_IPL can be used, as shown in
Example 15. These macros make use of the
SET_CPU_IPL macro.
For modification of the Interrupt 1 setting, the
INTERRUPT_PROTECT macro can be used. This
macro disables interrupts before executing the
desired expression, as shown in Example 16. This
macro is not distributed with the compiler.
the
CPU
© 2008 Microchip Technology Inc.
IPL,
the
macros
and