AT91SAM9G20B-CFU Atmel, AT91SAM9G20B-CFU Datasheet - Page 15

• Manufacturer Part Number: AT91SAM9G20B-CFU
• Description: IC MCU ARM9 247-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G20B-CFU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 247-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 400 MHz
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9G20-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7. Processor and Architecture
7.1
7.2
6384DS–ATARM–13-Jan-10
ARM926EJ-S Processor
Bus Matrix
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 32-Kbyte Data Cache, 32-Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
– Fixed-priority Arbitration
each quarter of the page
system flexibility
32-bit data interface
(Words)
AT91SAM9G20 Summary
15