AT90CAN128-16MU Atmel, AT90CAN128-16MU Datasheet - Page 326
![IC MCU AVR 128K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MU
Manufacturer Part Number
AT90CAN128-16MU
Description
IC MCU AVR 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, PS2, SPI, SRAM, USB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
3
Operating Supply Voltage
1.8 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
90C
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Quantity:
12 000
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Part Number:
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Manufacturer:
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24.5.1
326
AT90CAN32/64/128
Store Program Memory Control and Status Register – SPMCSR
grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be
changed through the serial or parallel programming interface.
Table 24-4.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the AT90CAN32/64/128 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while
the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ-
ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock
bit set, or if no SPM instruction is executed within four clock cycles.
Bit
Read/Write
Initial Value
BOOTRST
1
0
1. “1” means unprogrammed, “0” means programmed
SPMIE
Boot Reset Fuse
R/W
7
0
Reset Address
Reset Vector = Application Reset (address 0x0000)
Reset Vector = Boot Loader Reset (see
RWWSB
R
6
0
(1)
R
5
–
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
Table 24-6 on page
PGWRT
R/W
2
0
PGERS
R/W
1
0
334)
SPMEN
R/W
0
0
SPMCSR
7679H–CAN–08/08
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