AT90USB1286-AU Atmel, AT90USB1286-AU Datasheet - Page 260
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AT90USB1286-AU
Manufacturer Part Number
AT90USB1286-AU
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Specifications of AT90USB1286-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AVR USB
No. Of I/o's
48
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB1286-AU
Manufacturer:
SOUTH
Quantity:
650
Part Number:
AT90USB1286-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90USB1286-AUR
Manufacturer:
Atmel
Quantity:
747
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21.10.1
21.10.2
21.11 ID detection
260
AT90USB64/128
Peripheral mode
Host mode
Figure 21-16. Plug-in Detection Input Block Diagram
The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level :
The USB peripheral cannot attach to the bus while VBUS bit is not set.
The Host must use the UVCON pin to drive an external power switch or regulator that powers
the Vbus line. The UVCON pin is automatically asserted and set high by hardware when
UVCONE and VBUSREQ bits are set by firmware.
If a device connects (pull-up on DP or DM) within 300ms of Vbus delivery, the DCONNI flag will
rise. But, once VBUSREQ bit has been set, if no peripheral connection is detected within 300ms,
the BCERRI flag (and interrupt) will rise and Vbus delivery will be stopped (UVCON cleared).
If that behavior represents a limitation for the Host application, the following work-around may be
used :
The ID pin transition is detected thanks to the following architecture:
• The “Session_valid” signal is active high when the voltage on the VBUS pad is higher or
• The “Vbus_valid” signal is active high when the voltage on the VBUS pad is higher or equal to
• The VBUS status bit is set when VBUS is greater than “Vbus_valid”. The VBUS status bit is
• The VBUSTI flag is set each time the VBUS bit state changes.
1. UVCONE and VBUSREQ must be cleared
2. VBUSHWC must be set (to disable hardware control of UVCON pin)
3. PORTE,7 pin (alternate function of UVCON pin) must be set by firmware
4. a device connection will be detected thanks to the SRPI flag (that may usually be used
equal to 1.4V. If lower than 1.4V, the signal is not active.
4.4V. If lower than 4.4V, the signal is not active.
cleared when VBUS falls below “Session_valid” (hysteresis behavior).
to detect a DP/DM pulse sent by an OTG B-Device that requests a new session)
VBUS
Pad logic
VDD
VSS
Vbus_valid
Session_valid
VBus_pulsing
VBus_discharge
Logic
USBSTA.0
VBUS
7593K–AVR–11/09
VBUSTI
USBINT.0
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