PIC24FJ256DA210-I/PT Microchip Technology, PIC24FJ256DA210-I/PT Datasheet - Page 236

MCU PIC 16BIT FLASH 256K 100TQFP

PIC24FJ256DA210-I/PT

Manufacturer Part Number
PIC24FJ256DA210-I/PT
Description
MCU PIC 16BIT FLASH 256K 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets

Specifications of PIC24FJ256DA210-I/PT

Core Size
16-Bit
Program Memory Size
256KB (85.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
84
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
UART, SPI, USB, I2C, RS-485, RS-232
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
23
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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PIC24FJ256DA210 FAMILY
REGISTER 17-2:
DS39969B-page 236
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
URXISEL1
UTXISEL1
R/W-0
R/W-0
2:
Value of bit only affects the transmit properties of the module when the IrDA
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
UTXINV: IrDA
IREN = 0:
1 = UxTX is Idle ‘0’
0 = UxTX is Idle ‘1’
IREN = 1:
1 = UxTX is Idle ‘1’
0 = UxTX is Idle ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission is disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit is enabled, UxTX pin controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL0
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
controlled by port.
transmit buffer becomes empty
operations are completed
least one character open in the transmit buffer)
UxSTA: UARTx STATUS AND CONTROL REGISTER
(1)
®
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
Encoder Transmit Polarity Inversion bit
UTXISEL0
ADDEN
R/W-0
R/W-0
(2)
R-1, HSC
RIDLE
U-0
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
R-0, HSC
UTXBRK
PERR
(1)
UTXEN
R-0, HSC
R/W-0
FERR
(2)
®
 2010 Microchip Technology Inc.
x = Bit is unknown
encoder is enabled
R/C-0, HS
R-0, HSC
UTXBF
OERR
R-1, HSC
R-0, HSC
URXDA
TRMT
bit 8
bit 0

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