AT89C51ID2-SLRUM Atmel, AT89C51ID2-SLRUM Datasheet - Page 75

IC 8051 MCU 64K FLASH 44-PLCC

AT89C51ID2-SLRUM

Manufacturer Part Number
AT89C51ID2-SLRUM
Description
IC 8051 MCU 64K FLASH 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ID2-SLRUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI, TWI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
AT89C51ID2-SLRUMTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51ID2-SLRUM
Manufacturer:
Atmel
Quantity:
10 000
Registers
75
AT89C51ID2
Table 58. PCON Register
PCON (S87:h) Power configuration Register
Reset Value= XXXX 0000b
Number
Bit
7-5
7
-
4
3
2
1
0
Mnemonic Description
POF
GF1
GF0
Bit
IDL
PD
6
-
-
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
5
-
POF
4
GF1
3
GF0
2
PD
1
4289C–8051–11/05
IDL
0

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