ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 100

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5
8284A–AVR–10/10
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set
the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and
Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare
interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively,
the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according to operating mode
set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig-
nals are used by the Waveform Generator for handling the special cases of the extreme values
in some modes of operation
Figure 14-3
Figure 14-3. Output Compare Unit, Block Diagram
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
shows a block diagram of the Output Compare unit.
bottom
FOCn
top
OCRnx
(See ”Modes of Operation” on page
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMnX1:0
102.).
TCNTn
OCFnx (Int.Req.)
OCnx
100