PIC14000T-04/SO Microchip Technology, PIC14000T-04/SO Datasheet - Page 20
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PIC14000T-04/SO
Manufacturer Part Number
PIC14000T-04/SO
Description
IC MCU OTP 4KX14 A/D 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 14r
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC14000-04SO.pdf
(153 pages)
4.PIC14000-04SO.pdf
(5 pages)
Specifications of PIC14000T-04/SO
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
20
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
Slope A/D
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC14000
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
1
Operating Supply Voltage
2.7 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
14 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC14000T-04/SO
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC14000
4.2.2.4
This register contains the individual enable bits for the
Peripheral interrupts including A/D capture event, I
serial port, PORTC change and A/D capture timer
overflow, and external push button.
FIGURE 4-6:
DS40122B-page 20
bit7
CMIE
R/W
PIE1 REGISTER
R
—
PIE1 REGISTER
—
R
PBIE I
R/W
2
CIE
R/W
RCIE
R/W
ADCIE
R/W
Preliminary
2
C
OVFIE
R/W
bit0
OVFIE: A/D Counter Overflow Interrupt Enable
1 = Enables A/D counter overflow interrupt
0 = Disables A/D counter overflow interrupt
ADCIE: A/D Capture Interrupt Enable
1 = A/D capture interrupt is enabled
0 = A/D capture interrupt is disabled
RCIE:
1 = Enables RCIF interrupt on pins, RC<7:4>
0 = Disables RCIF interrupt
I
1 = Enables I
0 = Disables I
PBIE: External Pushbutton Interrupt Enable
1 = Enable PBTN (pushbutton) interrupt on OSC1/PBTN.
0 = Disable PBTN interrupt on OSC1/PBTN
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
CMIE: Programmable Reference Comparator Interrupt Enable
1 = Enable programmable reference comparator trip
0 = Disable programmable reference comparator trip
2
CIE: I
Note:
(Note this interrupt not available in HS mode).
Register:
Address:
POR value:
2
PORTC Interrupt on change Enable
C Port Interrupt Enable
INTCON<6> must be enabled to enable
any interrupt in PIE1.
2
2
CIF interrupt
CIF interrupt
PIE1
8Ch
00h
W:
R:
U:
1996 Microchip Technology Inc.
Writable
Readable
Unimplemented,
read as '0'