PIC16C63-04/SO Microchip Technology, PIC16C63-04/SO Datasheet - Page 141

• Manufacturer Part Number: PIC16C63-04/SO
• Description: IC MCU OTP 4KX14 PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63-04/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.8
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, status bit PD (STATUS<3>) is cleared,
status bit TO (STATUS<4>) is set, and the oscillator
driver is turned off. The I/O ports maintain the status
they had before the SLEEP instruction was executed
(driving high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
cuitry is drawing current from the I/O pin, and disable
external clocks. Pull all I/O pins, that are hi-impedance
inputs, high or low externally to avoid switching cur-
rents caused by floating inputs. The T0CKI input should
also be at V
The contribution from on-chip pull-ups on PORTB
should be considered.
The MCLR/V
(V
13.8.1
The device can wake from SLEEP through one of the
following events:
1.
2.
3.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO bit
is cleared if WDT time-out occurred (and caused wake-
up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1997 Microchip Technology Inc.
IHMC
External reset input on MCLR/V
Watchdog Timer Wake-up
enabled).
Interrupt from RB0/INT pin, RB port change, or
some peripheral interrupts.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode (SPI/I
CCP capture mode interrupt.
Parallel Slave Port read or write.
USART TX or RX (synchronous slave mode).
).
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
DD
PP
or V
pin must be at a logic high level
DD
SS
, or V
for lowest current consumption.
SS
, ensure no external cir-
PP
(if WDT
pin.
2
was
C).
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.8.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
SLEEP instruction, the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
tion of a SLEEP instruction, the device will imme-
diately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
WAKE-UP USING INTERRUPTS
PIC16C6X
DS30234D-page 141