PIC18LF4455-I/P Microchip Technology, PIC18LF4455-I/P Datasheet - Page 71

• Manufacturer Part Number: PIC18LF4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/P

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 35
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 5-2:
© 2007 Microchip Technology Inc.
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
Legend:
Note
File Name
(3)
(3)
(3)
(3)
(3)
1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I
2
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
C Slave mode only.
SPPIP
SPPIE
OSCFIP
OSCFIE
SPPIF
INTSRC
RDPU
OSCFIF
TRISD7
TRISC7
EEPGD
TRISB7
LATD7
LATC7
LATB7
Bit 7
RD7
RC7
RB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
(3)
(3)
(3)
(3)
TRISA6
LATA6
TRISD6
TRISC6
TRISB6
LATD6
LATC6
LATB6
RA6
CFGS
CMIP
CMIF
CMIE
Bit 6
ADIP
ADIF
ADIE
RD6
RC6
RB6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
(4)
(4)
TRISD5
TRISB5
TRISA5
LATD5
USBIP
USBIF
USBIE
LATB5
LATA5
RC5
RCIP
RCIF
RCIE
Bit 5
RD5
RB5
RA5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
PIC18F2455/2550/4455/4550
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
TRISD4
TRISB4
TRISA4
LATD4
LATB4
LATA4
RC4
FREE
TUN4
Bit 4
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
RD4
RB4
RA4
—
—
—
—
—
Preliminary
(6)
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
WRERR
TRISD3
TRISB3
TRISA3
LATD3
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
LATB3
LATA3
RE3
TUN3
Bit 3
RD3
RB3
RA3
—
—
—
—
—
(5)
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
EPOUTEN
HLVDIP
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISD2
TRISC2
HLVDIF
TRISE2
TRISB2
TRISA2
WREN
LATD2
LATC2
LATE2
LATB2
LATA2
RE2
TUN2
Bit 2
RD2
RC2
RB2
RA2
(3)
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISD1
TRISC1
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
TRISE1
TRISB1
TRISA1
LATD1
LATC1
LATE1
LATB1
LATA1
RE1
TUN1
Bit 1
RD1
RC1
RB1
RA1
WR
(3)
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TRISD0
TRISC0
TRISE0
TRISB0
TRISA0
LATD0
LATC0
LATE0
LATB0
LATA0
RE0
TUN0
Bit 0
RD0
RC0
RB0
RA0
RD
(3)
DS39632D-page 69
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
0000 0000
0000 0000
0000 0000
xx-0 x000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0--0 0000
---- -111
1111 1111
11-- -111
1111 1111
-111 1111
---- -xxx
xxxx xxxx
xx-- -xxx
xxxx xxxx
-xxx xxxx
0--- x000
xxxx xxxx
xxxx -xxx
xxxx xxxx
-x0x 0000
POR, BOR
Value on
on page
Details
54, 107
54, 103
54, 105
54, 106
54, 102
54, 104
54, 124
54, 122
54, 119
54, 116
54, 113
54, 124
54, 122
54, 119
54, 116
54, 113
54, 123
54, 122
54, 119
54, 116
54, 113
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
55, 169
53, 89
53, 89
53, 80
53, 81
54, 28