PIC18LF4455-I/P Microchip Technology, PIC18LF4455-I/P Datasheet - Page 315

• Manufacturer Part Number: PIC18LF4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/P

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 35
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.1.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
W
W
Q1
STANDARD INSTRUCTION SET
All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
=
=
10h
25h
ADD Literal to W
ADDLW
0 ≤ k ≤ 255
(W) + k → W
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
1
1
literal ‘k’
ADDLW
Read
0000
Q2
15h
k
1111
Process
Data
Q3
kkkk
Write to W
PIC18F2455/2550/4455/4550
Q4
kkkk
Preliminary
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
ADDWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + (f) → dest
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ADDWF
Read
0010
Q2
17h
0C2h
0D9h
0C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
DS39632D-page 313
ffff
destination
Write to
Q4
ffff