PIC18LF4455-I/P Microchip Technology, PIC18LF4455-I/P Datasheet - Page 225

• Manufacturer Part Number: PIC18LF4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/P

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 35
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

19.4.7
In I
reload value is placed in the lower seven bits of the
SSPADD register (Figure 19-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 19-19:
TABLE 19-3:
© 2007 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
CY
2
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
SSPM3:SSPM0
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
SCL
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
CY
* 2
PIC18F2455/2550/4455/4550
) on the
Control
Reload
Preliminary
CLKO
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BRG Down Counter
2
SSPADD<6:0>
C specification (which applies to rates greater than
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
00h
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
308 kHz
DS39632D-page 223
100 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)