PIC18LF4455-I/P Microchip Technology, PIC18LF4455-I/P Datasheet - Page 424

• Manufacturer Part Number: PIC18LF4455-I/P
• Description: IC PIC MCU FLASH 12KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/P

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 35
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
Timing Diagrams and Specifications ................................ 380
Top-of-Stack Access .......................................................... 58
TQFP Packages and Special Features ............................ 305
TSTFSZ ............................................................................ 347
Two-Speed Start-up ................................................. 285, 299
Two-Word Instructions
TXSTA Register
DS39632D-page 422
Synchronous Transmission ...................................... 254
Synchronous Transmission (Through TXEN) .......... 255
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 384
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 40
Transition for Wake from Sleep (HSPLL) ................... 39
Transition From RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 38
USB Signal ............................................................... 395
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 382
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 380
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................. 381
Reset, Watchdog Timer, Oscillator Start-up
Streaming Parallel Port Requirements
Timer0 and Timer1 External Clock
USB Full-Speed Requirements ................................ 395
USB Low-Speed Requirements ............................... 395
Example Cases .......................................................... 62
BRGH Bit ................................................................. 241
2
2
C Bus Data Requirements (Slave Mode) .............. 391
C Bus Start/Stop Bits Requirements ..................... 390
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 299
PRI_RUN Mode ................................................. 38
PRI_RUN Mode (HSPLL) .................................. 37
(All CCP Modules) ........................................... 385
Requirements ................................................... 394
Requirements ................................................... 394
(Master Mode, CKE = 0) .................................. 386
(Master Mode, CKE = 1) .................................. 387
(Slave Mode, CKE = 0) .................................... 388
(Slave Mode, CKE = 1) .................................... 389
Requirements ................................................... 392
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 383
(PIC18F4455/4550) ......................................... 396
Requirements ................................................... 384
2
2
C Bus Data Requirements ................ 393
C Bus Start/Stop Bits
DD
DD
) ........................................... 49
, V
DD
DD
DD
), Case 1 ....................... 48
), Case 2 ....................... 48
Rise T
PWRT
) .............. 48
Preliminary
U
Universal Serial Bus .......................................................... 63
USB. See Universal Serial Bus.
Address Register (UADDR) ..................................... 170
and Streaming Parallel Port ..................................... 183
Associated Registers ............................................... 184
Buffer Descriptor Table ............................................ 171
Buffer Descriptors .................................................... 171
Class Specifications and Drivers ............................. 186
Descriptors ............................................................... 186
Endpoint Control ...................................................... 169
Enumeration ............................................................ 186
External Pull-up Resistors ....................................... 167
External Transceiver ................................................ 165
Eye Pattern Test Enable .......................................... 167
Firmware and Drivers .............................................. 184
Frame Number Registers ........................................ 170
Frames .................................................................... 185
Internal Pull-up Resistors ......................................... 167
Internal Transceiver ................................................. 165
Internal Voltage Regulator ....................................... 167
Interrupts ................................................................. 177
Layered Framework ................................................. 185
Oscillator Requirements .......................................... 184
Output Enable Monitor ............................................. 167
Overview .......................................................... 163, 185
Ping-Pong Buffer Configuration ............................... 167
Power ...................................................................... 185
Power Modes ........................................................... 183
RAM ......................................................................... 170
Speed ...................................................................... 186
Status and Control ................................................... 164
Transfer Types ......................................................... 185
UFRMH:UFRML Registers ...................................... 170
Address Validation ........................................... 174
Assignment in Different
BDnSTAT Register (CPU Mode) ..................... 172
BDnSTAT Register (SIE Mode) ....................... 174
Byte Count ....................................................... 174
Example ........................................................... 171
Memory Map .................................................... 175
Ownership ....................................................... 171
Ping-Pong Buffering ........................................ 175
Register Summary ........................................... 176
Status and Configuration ................................. 171
and USB Transactions ..................................... 177
Bus Power Only ............................................... 183
Dual Power with Self-Power
Self-Power Only ............................................... 183
Memory Map .................................................... 170
Buffering Modes ...................................... 176
Dominance .............................................. 183
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