AT89C51RC2-SLSUM Atmel, AT89C51RC2-SLSUM Datasheet - Page 64

IC 8051 MCU FLASH 32K 44PLCC

AT89C51RC2-SLSUM

Manufacturer Part Number
AT89C51RC2-SLSUM
Description
IC 8051 MCU FLASH 32K 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51RC2-SLSUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
60MHz
Interface Type
SPI/UART
Total Internal Ram Size
1.25KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1280 B
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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Keyboard Interface
Interrupt
Power Reduction Mode
64
AT89C51RB2/RC2
The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS,
the Keyboard Level Selection register (Table 53), KBE, the Keyboard interrupt Enable
register (Table 52), and KBF, the Keyboard Flag register (Table 51).
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or dis-
able of the keyboard interrupt (see Figure 23). As detailed in Figure 24 each keyboard
input has the capability to detect a programmable level according to KBLS. x bit value.
Level detection is then reported in interrupt flags KBF. x that can be masked by software
using KBE. x bits.
This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allow
usage of P1 inputs for other purpose.
Figure 23. Keyboard Interface Block Diagram
Figure 24. Keyboard Input Circuitry
P1 inputs allow exit from idle and power down modes as detailed in Section “Power-
down Mode”, page 82.
P1:x
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
V
CC
Internal Pull-up
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
KBLS. x
0
1
KBF. x
KBE. x
IEN1
KBD
Keyboard Interface
Interrupt Request
KBDIT
4180E–8051–10/06

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