AT89C51RC2-SLSUM Atmel, AT89C51RC2-SLSUM Datasheet - Page 16
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AT89C51RC2-SLSUM
Manufacturer Part Number
AT89C51RC2-SLSUM
Description
IC 8051 MCU FLASH 32K 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RB2-RLTIL.pdf
(127 pages)
Specifications of AT89C51RC2-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
60MHz
Interface Type
SPI/UART
Total Internal Ram Size
1.25KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1280 B
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51RC2-SLSUM
Manufacturer:
Atmel
Quantity:
897
Part Number:
AT89C51RC2-SLSUM
Manufacturer:
ATMEL
Quantity:
20 000
Enhanced Features
X2 Feature
Description
16
AT89C51RB2/RC2
In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new fea-
tures, which are
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•
•
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The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
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•
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripherals is first divided by 2 before being used by
the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid glitches when switching from X2 to X1 mode. Figure 6 shows
the switching mode waveforms.
Figure 5. Clock Generation Diagram
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
SPI interface
4-level interrupt priority system
power-off flag
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the timer 2
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
XTAL1
FXTAL
:
2
XTAL1:2
CKCON0
X2
0
1
F
OSC
8 bit Prescaler
CKRL
4180E–8051–10/06
F
F
CLK CPU
CLK PERIPH