PIC16LC924-04I/L Microchip Technology, PIC16LC924-04I/L Datasheet - Page 75

• Manufacturer Part Number: PIC16LC924-04I/L
• Description: IC MCU OTP 4KX14 LCD DVR 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC924-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Core: PIC
• Processor Series: PIC16LC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 176 B
• Data Rom Size: 176 B
• On-chip Adc: 8 bit, 5 Channel
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 6 V
• Mounting Style: SMD/SMT
• Height: 4.06 mm
• Interface Type: I2C, SPI
• Length: 24.33 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Width: 24.33 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The received address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
FIGURE 11-19: I
SDA
SCL
SSPIF (PIR1<3>)
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
5
6
7
R/W=0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
PIC16C9XX
D3
5
D2
6
D1
7
DS30444E - page 75
D0
8
ACK
9
Bus Master
terminates
transfer
P