AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 234
![MCU AVR 64K FLASH 16MHZ 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT90CAN64-16AUR
Manufacturer Part Number
AT90CAN64-16AUR
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheet
1.AT90CAN32-16AUR.pdf
(428 pages)
Specifications of AT90CAN64-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
4 KB
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19. Controller Area Network - CAN
19.1
19.2
19.2.1
234
Features
CAN Protocol
AT90CAN32/64/128
Principles
The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very
high level of security. The AT90CAN32/64/128 CAN controller is fully compatible with the CAN
Specification 2.0 Part A and Part B. It delivers the features required to implement the kernel of
the CAN bus protocol according to the ISO/OSI Reference Model:
• The Data Link Layer
• The Physical Layer
The CAN controller is able to handle all types of frames (Data, Remote, Error and Overload) and
achieves a bitrate of 1 Mbit/s.
The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO
11519-2 for low speed.
CAN is based on a broadcast communication mechanism. This broadcast communication is
achieved by using a message oriented transmission protocol. These messages are identified by
using a message identifier. Such a message identifier has to be unique within the whole network
and it defines not only the content but also the priority of the message.
The priority at which a message is transmitted compared to another less urgent message is
specified by the identifier of each message. The priorities are laid down during system design in
the form of corresponding binary values and cannot be changed dynamically. The identifier with
the lowest binary number has the highest priority.
Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node
observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism,
• Full Can Controller
• Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B
• 15 MOb (Message Object) with their own:
• 1 Mbit/s Maximum Transfer Rate at 8 MHz
• TTC Timer
• Listening Mode (for Spying or Autobaud)
– 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B)
– 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.0 B)
– 8 Bytes Data Buffer (Static Allocation)
– Tx, Rx, Frame Buffer or Automatic Reply Configuration
– Time Stamping
- the Logical Link Control (LLC) sublayer
- the Medium Access Control (MAC) sublayer
- the Physical Signalling (PLS) sublayer
- not supported - the Physical Medium Attach (PMA)
- not supported - the Medium Dependent Interface (MDI)
7679H–CAN–08/08
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