AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 159
AT90CAN64-16AUR
Manufacturer Part Number
AT90CAN64-16AUR
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheet
1.AT90CAN32-16AUR.pdf
(428 pages)
Specifications of AT90CAN64-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
4 KB
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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14.9.2
14.9.3
7679H–CAN–08/08
Timer/Counter2 Register – TCNT2
Output Compare Register A – OCR2A
Table 14-4
rect PWM mode.
Table 14-4.
Note:
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
14-5.
Table 14-5.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
COM2A1
CS22
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See
page 153
shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
R/W
R/W
7
0
7
0
COM2A0
CS21
for more details.
0
0
1
1
0
0
1
1
0
1
0
1
R/W
R/W
6
0
6
0
Description
Normal port operation, OC2A disconnected.
Reserved
Clear OC2A on compare match when up-counting.
Set OC2A on compare match when downcounting.
Set OC2A on compare match when up-counting.
Clear OC2A on compare match when downcounting.
R/W
R/W
5
0
5
0
CS20
0
1
0
1
0
1
0
1
R/W
R/W
4
0
4
0
OCR2A[7:0]
TCNT2[7:0]
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
clk
clk
T2S
T2S
T2S
T2S
T2S
T
T
2
2
R/W
R/W
S
S
/256 (From prescaler)
/1024 (From prescaler)
3
0
3
0
/(No prescaling)
/8 (From prescaler)
/32 (From prescaler)
/64 (From prescaler)
/128 (From prescaler)
R/W
R/W
2
0
2
0
AT90CAN32/64/128
R/W
R/W
1
0
1
0
(1)
“Phase Correct PWM Mode” on
R/W
R/W
0
0
0
0
OCR2A
TCNT2
Table
159
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