DSPIC33FJ64MC706-I/PT Microchip Technology, DSPIC33FJ64MC706-I/PT Datasheet - Page 39
![IC DSPIC MCU/DSP 64K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ64MC706-I/PT
Manufacturer Part Number
DSPIC33FJ64MC706-I/PT
Description
IC DSPIC MCU/DSP 64K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC706-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Embedded Interface Type
ECAN, I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To
Package
64TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
53
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
32-chx10-bit|32-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC706-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC33FJ64MC706-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 9-6:
TABLE 9-7:
© 2005 Microchip Technology Inc.
Assembly
ASR
ASR
ASR
ASR
LSR
LSR
LSR
LSR
RLC
RLC
RLNC
RLNC
RRC
RRC
RRNC
RRNC
SL
SL
SL
SL
BCLR
BCLR
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTST
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
BTSTS.C
BTSTS.Z
FBCL
FF1L
FF1R
Note:
Note:
Assembly
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
Bit positions are specified by bit4 (0:15) for word operations.
Syntax
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
Syntax
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wnd
Ws,Wnd
Ws,Wnd
ROTATE/SHIFT INSTRUCTIONS
BIT INSTRUCTIONS
Destination = arithmetic right shift f
Wd = arithmetic right shift Ws
Wnd = arithmetic right shift Wb by lit4
Wnd = arithmetic right shift Wb by Wns
Destination = logical right shift f
Wd = logical right shift Ws
Wnd = logical right shift Wb by lit4
Wnd = logical right shift Wb by Wns
Destination = rotate left through Carry f
Wd = rotate left through Carry Ws
Destination = rotate left (no Carry) f
Wd = rotate left (no Carry) Ws
Destination = rotate right through Carry f
Wd = rotate right through Carry Ws
Destination = rotate right (no Carry) f
Wd = rotate right (no Carry) Ws
Destination = left shift f
Wd = left shift Ws
Wnd = left shift Wb by lit4
Wnd = left shift Wb by Wns
Bit clear f
Bit clear Ws
Bit set f
Bit set Ws
Write C bit to Ws<Wb>
Write SZ bit to Ws<Wb>
Bit toggle f
Bit toggle Ws
Bit test f
Bit test Ws to C
Bit test Ws to SZ
Bit test Ws<Wb> to C
Bit test Ws<Wb> to SZ
Bit test f then set f
Bit test Ws to C then set Ws
Bit test Ws to SZ then set Ws
Find bit change from left (MSb) side
Find first one from left (MSb) side
Find first one from right (LSb) side
Preliminary
Description
Description
dsPIC33F
Words
Words
DS70155C-page 37
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1