ATMEGA329V-8MUR Atmel, ATMEGA329V-8MUR Datasheet - Page 316
ATMEGA329V-8MUR
Manufacturer Part Number
ATMEGA329V-8MUR
Description
MCU AVR 32K FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA329-16AU.pdf
(392 pages)
Specifications of ATMEGA329V-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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27.8.8
27.8.9
27.8.10
316
ATmega329/3290/649/6490
Reset Register
Programming Enable Register
Programming Command Register
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset
as long as there is a high value present in the Reset Register. Depending on the Fuse settings
for the clock options, the part will remain reset for a Reset Time-out period (refer to
Sources” on page
not latched, so the reset will take place immediately, as shown in
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-
tents of the register is equal to the programming enable signature, programming via the JTAG
port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when
leaving Programming mode.
Figure 27-14. Programming Enable Register
The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming commands, and to serially shift out the result of the previous command, if any. The
JTAG Programming Instruction Set is shown in
in the programming commands is illustrated in
27) after releasing the Reset Register. The output from this Data Register is
TDO
TDI
D
A
T
A
0xA370
=
ClockDR & PROG_ENABLE
Figure
Table
D
Q
27-16.
27-16. The state sequence when shifting
Programming Enable
Figure 25-2 on page
2552K–AVR–04/11
253.
“Clock
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