ATMEGA329V-8MUR Atmel, ATMEGA329V-8MUR Datasheet - Page 254
ATMEGA329V-8MUR
Manufacturer Part Number
ATMEGA329V-8MUR
Description
MCU AVR 32K FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA329-16AU.pdf
(392 pages)
Specifications of ATMEGA329V-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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25.4.2
25.4.3
25.4.4
25.4.5
25.5
25.5.1
254
Boundary-scan Related Register in I/O Memory
ATmega329/3290/649/6490
IDCODE; 0x1
SAMPLE_PRELOAD; 0x2
AVR_RESET; 0xC
BYPASS; 0xF
MCUCR – MCU Control Register
Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
The active states are:
•
•
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
Bit
0x35 (0x55)
Read/Write
Initial Value
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
JTD
R/W
7
0
R
6
–
0
R
5
–
0
PUD
R/W
4
0
R
3
–
0
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
2552K–AVR–04/11
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