ATMEGA329V-8MUR Atmel, ATMEGA329V-8MUR Datasheet - Page 26
ATMEGA329V-8MUR
Manufacturer Part Number
ATMEGA329V-8MUR
Description
MCU AVR 32K FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA329-16AU.pdf
(392 pages)
Specifications of ATMEGA329V-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8.1.3
26
Clock Systems and their Distribution
ATmega329/3290/649/6490
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
LCD Controller
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
I/O
is halted, enabling USI start condition detection in all sleep modes.
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
General I/O
35. The clock systems are detailed below.
Modules
External Clock
clk
clk
ASY
I/O
Control Unit
AVR Clock
Multiplexer
Clock
Source clock
Oscillator
Crystal
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Crystal Oscillator
Watchdog clock
Low-frequency
Watchdog Timer
RAM
Watchdog
Oscillator
“Power Manage-
Calibrated RC
Flash and
EEPROM
2552K–AVR–04/11
Oscillator
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