PIC18F26J11-I/ML Microchip Technology, PIC18F26J11-I/ML Datasheet - Page 49
![IC PIC MCU FLASH 64K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F26J11-I/ML
Manufacturer Part Number
PIC18F26J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26J11-I/ML
Manufacturer:
MOLEX
Quantity:
1 001
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 49 of 528
- Download datasheet (8Mb)
On devices that support it, the Deep Sleep mode is
entered by:
• Setting the REGSLP (WDTCON<7>) bit (the
• Clearing the IDLEN bit (the default state on device
• Setting the DSEN bit (DSCONH<7>)
• Executing the SLEEP instruction immediately after
In order to minimize the possibility of inadvertently enter-
ing Deep Sleep, the DSEN bit is cleared in hardware
two instruction cycles after having been set. Therefore,
in order to enter Deep Sleep, the SLEEP instruction must
be executed in the immediate instruction cycle after set-
ting DSEN. If DSEN is not set when Sleep is executed,
the device will enter conventional Sleep mode instead.
During Deep Sleep, the core logic circuitry of the
microcontroller is powered down to reduce leakage
current. Therefore, most peripherals and functions of
the microcontroller become unavailable during Deep
Sleep. However, a few specific peripherals and func-
tions are powered directly from the V
the microcontroller, and therefore, can continue to
function in Deep Sleep.
Entering Deep Sleep mode clears the DSWAKEL regis-
ter. However, if the Real-Time Clock and Calendar
(RTCC) is enabled prior to entering Deep Sleep, it will
continue to operate uninterrupted.
The device has dedicated low-power Brown-out Reset
(DSBOR) and Watchdog Timer Reset (DSWDT) for
monitoring voltage and time-out events in Deep Sleep.
The DSBOR and DSWDT are independent of the stan-
dard BOR and WDT used with other power-managed
modes (Run, Idle and Sleep).
When a wake event occurs in Deep Sleep mode (by
MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or
DSWDT), the device will exit Deep Sleep mode and
perform a Power-on Reset (POR). When the device is
released from Reset, code execution will resume at the
device’s Reset vector.
3.6.1
Because V
voltage while in Deep Sleep mode, SRAM data could
be lost in Deep Sleep. Exiting Deep Sleep mode
causes a POR; as a result, most Special Function
Registers will reset to their default POR values.
Applications needing to save a small amount of data
throughout a Deep Sleep cycle can save the data to the
general purpose DSGPR0 and DSGPR1 registers. The
contents of these registers are preserved while the
device is in Deep Sleep, and will remain valid throughout
an entire Deep Sleep entry and wake-up sequence.
© 2009 Microchip Technology Inc.
default state on device Reset)
Reset)
setting DSEN (no delay in between)
DDCORE
PREPARING FOR DEEP SLEEP
could fall below the SRAM retention
DD
supply rail of
PIC18F46J11 FAMILY
3.6.2
During Deep Sleep, the general purpose I/O pins will
retain their previous states.
Pins that are configured as inputs (TRIS bit set) prior to
entry into Deep Sleep will remain high-impedance
during Deep Sleep.
Pins that are configured as outputs (TRIS bit clear)
prior to entry into Deep Sleep will remain as output pins
during Deep Sleep. While in this mode, they will drive
the output level determined by their corresponding LAT
bit at the time of entry into Deep Sleep.
When the device wakes back up, the I/O pin behavior
depends on the type of wake-up source.
If the device wakes back up by an RTCC alarm, INT0
interrupt, DSWDT or ULPWU event, all I/O pins will
continue to maintain their previous states, even after the
device has finished the POR sequence and is executing
application code again. Pins configured as inputs during
Deep Sleep will remain high-impedance, and pins con-
figured as outputs will continue to drive their previous
value.
After waking up, the TRIS and LAT registers will be
reset, but the I/O pins will still maintain their previous
states. If firmware modifies the TRIS and LAT values for
the I/O pins, they will not immediately go to the newly
configured states. Once the firmware clears the
RELEASE bit (DSCONL<0>), the I/O pins will be
“released”. This causes the I/O pins to take the states
configured by their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) circuit is enabled, and
V
olds, the I/O pins will be immediately released similar to
clearing the RELEASE bit. All previous state informa-
tion will be lost, including the general purpose DSGPR0
and DSGPR1 contents. See Section 3.6.5 “Deep
Sleep Brown Out Reset (DSBOR)” for additional
details about this scenario.
If a MCLR Reset event occurs during Deep Sleep, the I/O
pins will also be released automatically, but in this case,
the DSGPR0 and DSGPR1 contents will remain valid.
In all other Deep Sleep wake-up cases, application
firmware needs to clear the RELEASE bit in order to
reconfigure the I/O pins.
DD
drops below the DSBOR and V
I/O PINS DURING DEEP SLEEP
DD
DS39932C-page 49
rail POR thresh-
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