PIC18F26J11-I/ML Microchip Technology, PIC18F26J11-I/ML Datasheet - Page 315
![IC PIC MCU FLASH 64K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F26J11-I/ML
Manufacturer Part Number
PIC18F26J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26J11-I/ML
Manufacturer:
MOLEX
Quantity:
1 001
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 315 of 528
- Download datasheet (8Mb)
18.5.17.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• The Start condition is aborted
• The BCLxIF flag is set
• The MSSP module is reset to its inactive state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the BRG is loaded from SSPxADD<6:0> and counts
down to 0. If the SCLx pin is sampled low while SDAx
is high, a bus collision occurs because it is assumed
that another master is attempting to drive a data ‘1’
during the Start condition.
FIGURE 18-28:
© 2009 Microchip Technology Inc.
(Figure 18-28)
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
SDAx or SCLx is sampled low at the beginning
of the Start condition (Figure 18-28).
SCLx is sampled low before SDAx is asserted
low (Figure 18-29).
Bus Collision During a Start
Condition
condition if SDAx = 1, SCLx = 1
Set SEN, enable Start
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx goes low before the SEN bit is set.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
Set BCLxIF,
SSPxIF and BCLxIF are
cleared in software
PIC18F46J11 FAMILY
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 18-30). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The BRG is then reloaded and counts
down to 0. If the SCLx pin is sampled as ‘0’ during this
time, a bus collision does not occur. At the end of the
BRG count, the SCLx pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
MSSPx module reset into Idle state.
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared in software
DS39932C-page 315
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