PIC18F26J11-I/ML Microchip Technology, PIC18F26J11-I/ML Datasheet - Page 263
![IC PIC MCU FLASH 64K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F26J11-I/ML
Manufacturer Part Number
PIC18F26J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26J11-I/ML
Manufacturer:
MOLEX
Quantity:
1 001
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 263 of 528
- Download datasheet (8Mb)
17.5.8
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
17.5.8.1
If the Fail-Safe Clock Monitor (FSCM) is enabled, a
clock
power-managed RC_RUN mode and the OSCFIF bit of
TABLE 17-5:
© 2009 Microchip Technology Inc.
INTCON
RCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
TRISC
TMR1L
TMR1H
TCLKCON
T1CON
TMR2
T2CON
PR2
TMR3L
TMR3H
T3CON
CCPR1L
CCPR1H
CCP1CON
ECCP1AS
ECCP1DEL
Legend:
Note 1:
Name
failure
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
These bits are only available on 44-pin devices.
OPERATION IN POWER-MANAGED
MODES
Timer1 Register Low Byte
Timer1 Register High Byte
Timer2 Register
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
Operation with Fail-Safe
Clock Monitor (FSCM)
TMR1CS1
TMR3CS1
GIE/GIEH
PMPIF
PMPIE
PMPIP
P1RSEN
OSCFIE
OSCFIP
OSCFIF
TRISC7
P1M1
IPEN
Bit 7
will
—
—
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
(1)
(1)
(1)
force
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
PEIE/GIEL
TMR1CS0
TMR3CS0
SBOREN
TRISC6
P1DC6
CM2IE
CM2IP
CM2IF
P1M0
ADIE
ADIP
Bit 6
ADIF
the
—
device
T1CKPS1
T3CKPS1
TMR0IE
TRISC5
DC1B1
P1DC5
CM1IF
CM1IE
CM1IP
RCIF
RCIE
RCIP
Bit 5
—
—
into
the
T1CKPS0
T3CKPS0
TRISC4
T1RUN
DC1B0
P1DC4
INT0IE
TXIE
TXIP
Bit 4
TXIF
RI
—
—
—
PIC18F46J11 FAMILY
the PIR2 register will be set. The ECCPx will then be
clocked from the internal oscillator clock source, which
may have a different clock frequency than the primary
clock.
17.5.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible
modules used on other PIC18 and PIC16 devices.
T1OSCEN
PSS1AC1
CCP1M3
TRISC3
BCL1IF
BCL1IE
BCL1IP
P1DC3
RABIE
SSPIE
SSPIP
SSPIF
Bit 3
TO
—
—
EFFECTS OF A RESET
PSS1AC0 PSS1BD1 PSS1BD0
T1SYNC
T3SYNC
CCP1M2
with
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
P1DC2
LVDIE
LVDIP
LVDIF
Bit 2
PD
—
previous, non-enhanced
T3CCP2
CCP1M1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
INT0IF
P1DC1
RD16
RD16
Bit 1
POR
TMR1ON
TMR3ON
DS39932C-page 263
T3CCP1
CCP1M0
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISC0
P1DC0
RABIF
Bit 0
BOR
on page:
Values
Reset
ECCP
63
64
65
65
65
65
65
65
66
64
64
87
64
64
64
64
67
67
67
65
65
65
64
65
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