PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 201
![IC PIC MCU FLASH 16KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65J90-I/PT
Manufacturer Part Number
PIC18F65J90-I/PT
Description
IC PIC MCU FLASH 16KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F63J90-IPT.pdf
(416 pages)
4.PIC18F63J90-IPT.pdf
(22 pages)
5.PIC18F63J90-IPT.pdf
(4 pages)
6.PIC18F63J90-IPT.pdf
(6 pages)
7.PIC18F63J90-IPT.pdf
(6 pages)
8.PIC18F63J90-IPT.pdf
(12 pages)
9.PIC18F85J90-IPT.pdf
(411 pages)
Specifications of PIC18F65J90-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
51
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65J90-I/PT
Manufacturer:
VISHAY
Quantity:
2 400
Company:
Part Number:
PIC18F65J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F65J90-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F63J90-IPT PDF datasheet #3
- PIC18F63J90-IPT PDF datasheet #4
- PIC18F63J90-IPT PDF datasheet #5
- PIC18F63J90-IPT PDF datasheet #6
- PIC18F63J90-IPT PDF datasheet #7
- PIC18F63J90-IPT PDF datasheet #8
- PIC18F85J90-IPT PDF datasheet #9
- Current page: 201 of 411
- Download datasheet (7Mb)
16.4.2
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
16.4.3
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
• The overflow bit, SSPOV (SSPCON1<6>), was
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF is set. The BF bit is
cleared by reading the SSPBUF register, while bit
SSPOV is cleared through software.
© 2007 Microchip Technology Inc.
clock = (F
Stop bit interrupts enabled
Stop bit interrupts enabled
slave is Idle
before the transfer was received.
set before the transfer was received.
2
2
2
2
2
2
C Master mode,
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode,
2
C Slave mode hardware will always generate an
OPERATION
SLAVE MODE
OSC
/4) x (SSPADD + 1)
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
Preliminary
2
C
PIC18F85J90 FAMILY
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter 100 and
parameter 101.
16.4.3.1
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is com-
pared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match and the BF and SSPOV bits are
clear, the following events occur:
1.
2.
3.
4.
In 10-Bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2
C specification, as well as the requirement of the
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSP Interrupt Flag bit, SSPIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear UA bit.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (SSPIF and
BF bits are set).
Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
Addressing
DS39770B-page 199
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