ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 95

• Manufacturer Part Number: ATMEGA8L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 28DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Timer/Counter
Register Description
Timer/Counter 1 Control
Register A – TCCR1A
2486O–AVR–10/04
Figure 44. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COM1A1:0: Compare Output Mode for channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for channel B
The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B
respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A
output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port
functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-
ister (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable
the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is
dependent of the WGM13:0 bits setting. Table 36 shows the COM1x1:0 bit functionality
when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM).
Table 36. Compare Output Mode, Non-PWM
(PC and PFC PWM)
and ICFn
Bit
Read/Write
Initial Value
(CTC and FPWM)
COM1A1/
TOVn
(Update at TOP)
COM1B1
TCNTn
TCNTn
OCRnx
as TOP)
(clk
0
0
1
1
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1
R/W
7
0
COM1A0/
COM1B0
0
1
0
1
COM1A0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match
Clear OC1A/OC1B on Compare Match (Set output to low level)
Set OC1A/OC1B on Compare Match (Set output to high level)
COM1B1
R/W
5
0
COM1B0
R/W
4
0
TOP
TOP
FOC1A
W
3
0
FOC1B
W
2
0
BOTTOM
clk_I/O
TOP - 1
New OCRnx Value
WGM11
ATmega8(L)
R/W
/8)
1
0
WGM10
R/W
0
0
BOTTOM + 1
TOP - 2
TCCR1A
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