ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 168

• Manufacturer Part Number: ATMEGA8L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 28DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TWI Register Description
TWI Bit Rate Register – TWBR
TWI Control Register – TWCR
168
ATmega8(L)
Interrupt Flag is asserted. At all other times, the TWSR contains a special status code
indicating that no relevant status information is available. As long as the TWINT Flag is
set, the SCL line is held low. This allows the application software to complete its tasks
before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
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•
•
•
•
•
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• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a
frequency divider which generates the SCL clock frequency in the Master modes. See
“Bit Rate Generator Unit” on page 167 for calculating bit rates.
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to
initiate a Master access by applying a START condition to the bus, to generate a
Receiver acknowledge, to generate a stop condition, and to control halting of the bus
while the data to be written to the bus are written to the TWDR. It also indicates a write
collision if data is attempted written to TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects appli-
cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will
jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is
stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note
that this flag is not automatically cleared by hardware when executing the interrupt rou-
tine. Also note that clearing this flag starts the operation of the TWI, so all accesses to
the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-
ter (TWDR) must be complete before clearing this flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
After the TWI has transmitted a START/REPEATED START condition.
After the TWI has transmitted SLA+R/W.
After the TWI has transmitted an address byte.
After the TWI has lost arbitration.
After the TWI has been addressed by own slave address or general call.
After the TWI has received a data byte.
After a STOP or REPEATED START has been received while still addressed as a
Slave.
When a bus error has occurred due to an illegal START or STOP condition.
TWBR7
TWINT
R/W
R/W
7
0
7
0
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
R
3
0
3
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
2486O–AVR–10/04
TWBR
TWCR