ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 100

• Manufacturer Part Number: ATMEGA8L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 28DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Capture Register 1 –
ICR1H and ICR1L
Timer/Counter Interrupt Mask
Register – TIMSK
100
ATmega8(L)
(1)
The Input Capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary High byte Register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the ICF1
Flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the
OCF1A Flag, located in TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the
OCF1B Flag, located in TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 44) is executed when the TOV1 Flag, located
in TIFR, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only
Timer1 bits are described in this section. The remaining bits are described in their
respective timer sections.
OCIE2
R/W
R/W
7
0
7
0
TOIE2
R/W
R/W
6
0
6
0
TICIE1
R/W
R/W
5
0
5
0
OCIE1A
R/W
R/W
4
0
4
0
ICR1[15:8]
ICR1[7:0]
OCIE1B
R/W
R/W
3
0
3
0
TOIE1
R/W
R/W
2
0
2
0
R/W
R
1
0
1
–
0
TOIE0
R/W
R/W
0
0
0
0
2486O–AVR–10/04
ICR1H
ICR1L
TIMSK