ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 237
![MCU AVR 8K FLASH 16MHZ 28-PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA8A-PU
Manufacturer Part Number
ATMEGA8A-PU
Description
MCU AVR 8K FLASH 16MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8A-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.7.12
24.7.13
24.7.14
8159D–AVR–02/11
Reading the Signature Bytes
Reading the Calibration Byte
Parallel Programming Characteristics
The algorithm for reading the Signature bytes is as follows (refer to
page 232
The algorithm for reading the Calibration bytes is as follows (refer to
page 232
Figure 24-4. Parallel Programming Timing, Including some General Timing Requirements
Figure 24-5. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
1. A: Load Command “0000 1000”.
2. B: Load Address Low byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
1. A: Load Command “0000 1000”.
2. B: Load Address Low byte, (0x00 - 0x03).
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
PAGEL
XTAL1
(DATA, XA0/1, BS1, BS2)
DATA
BS1
XA0
XA1
1. The timing requirements shown in
for details on Command and Address loading):
for details on Command and Address loading):
ing operation.
Data & Contol
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
XTAL1
(LOW BYTE)
WR
t
t
BVPH
DVXH
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
XHXL
PHPL
Figure 24-4
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
(i.e., t
t
BVWL
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
t
WL WH
t
XLPH
WLRL
, t
LOAD DATA
XHXL
“Programming the Flash” on
“Programming the Flash” on
, and t
t
PLXH
t
WLBX
XLDX
ATmega8A
LOAD ADDRESS
(LOW BYTE)
) also apply to load-
ADDR1 (Low Byte)
t
WLRH
(1)
237
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