DSPIC30F2010-20E/SP Microchip Technology, DSPIC30F2010-20E/SP Datasheet - Page 119

• Manufacturer Part Number: DSPIC30F2010-20E/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.8
The analog input model of the 10-bit ADC is shown in
Figure 18-3. The total sampling time for the A/D is a
function of the internal amplifier settling time, device
V
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
verter, the maximum recommended source imped-
ance, R
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 18-3:
© 2006 Microchip Technology Inc.
DD
SS
Note: C
and the holding capacitor charge time.
) impedance combine to directly affect the time
S
A/D Acquisition Requirements
, is 5 k . After the analog input channel is
Legend: C
PIN
VA
value depends on device package and is not tested. Effect of C
Rs
IC
), and the internal sampling switch
V
I leakage
R
R
C
ANx
PIN
T
IC
SS
HOLD
C
ADC ANALOG INPUT MODEL
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
HOLD
S
HOLD
), the interconnect
) must be allowed
. The combined
V
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
IC
500 nA
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the A/D con-
verter. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Electrical Specifications for T
requirements.
250
PIN
SAMP
negligible if Rs
Sampling
Switch
, between conversions to allow each sam-
R
SS
dsPIC30F2010
R
SS
V
5 k .
SS
C
= DAC capacitance
= 4.4 pF
HOLD
3 k
AD
AD
DS70118G-page 117
period of sampling
and sample time