PIC16CE625-04E/SS Microchip Technology, PIC16CE625-04E/SS Datasheet - Page 63

• Manufacturer Part Number: PIC16CE625-04E/SS
• Description: IC MCU OTP 2KX14 EE COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

10.8
The Power-down mode is entered by executing a
SLEEP
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin, and the com-
parators and V
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at V
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
10.8.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note 1:
INSTRUCTION FLOW
1999 Microchip Technology Inc.
Note:
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT(4)
External reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
2:
3:
4:
INT pin
SLEEP
instruction.
OSC1
Power-Down Mode (SLEEP)
WAKE-UP FROM SLEEP
PC
XT, HS or LP oscillator mode assumed.
T
GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
OST
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
REF
Inst(PC - 1)
was executed (driving high, low, or
PC
should be disabled. I/O pins that are
OSC
(drawing not to scale) This delay does not occur for RC osc mode.
DD
Q1 Q2 Q3 Q4
Inst(PC + 1)
or V
SLEEP
PC+1
SS
, with no external
Q1
Processor in
SLEEP
DD
IHMC
or V
PC+2
).
SS
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
The first event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset. PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT wake-up occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
rupt address (0004h). In cases where the execution of
the instruction following
user should have an
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
PC+2
Note:
SLEEP
Interrupt Latency
Dummy cycle
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from sleep. The
sleep instruction is completely executed.
instruction and then branches to the inter-
PC + 2
instruction is being executed, the
SLEEP
NOP
PIC16CE62X
Q1 Q2 Q3 Q4
SLEEP
Inst(0004h)
Dummy cycle
after the
0004h
instruction. If the GIE bit is
is not desirable, the
SLEEP
DS40182C-page 63
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h
instruction.