PIC16CE625-04E/SS Microchip Technology, PIC16CE625-04E/SS Datasheet - Page 26

• Manufacturer Part Number: PIC16CE625-04E/SS
• Description: IC MCU OTP 2KX14 EE COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PIC16CE62X
5.2
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A ’1’ in
the TRISB register puts the corresponding output driver
in a high impedance mode. A ’0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
( 200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins of RB<7:4> are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 5-5:
DS40182C-page 26
Set RBIF
Data Bus
WR PORTB
WR TRISB
RBPU
RB<7:6> in serial programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
(1)
From other
RB<7:4> pins
PORTB and TRISB Registers
(OPTION<7>).
(1)
RD TRISB
RD PORTB
BLOCK DIAGRAM OF
RB<7:4> PINS
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
Q
Q
Latch
EN
EN
D
D
TTL
Input
Buffer
weak
pull-up
V
RD Port
P
DD
ST
Buffer
I/O pin
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implement-
ing Wake-Up on Key Strokes”.)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
Data Bus
WR TRISB
WR PORTB
RBPU
Note:
RB0/INT
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
(1)
(OPTION<7>).
(1)
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
BLOCK DIAGRAM OF
RB<3:0> PINS
RD TRISB
RD PORTB
Data Latch
D
D
CK
CK
ST
Buffer
Q
Q
1999 Microchip Technology Inc.
Q
EN
TTL
Input
Buffer
D
weak
pull-up
V
P
DD
RD Port
I/O pin