ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 158

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.10.3
19.10.3.1
19.10.3.2
19.10.4
158
ATtiny261/461/861
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
Table 19-5.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
Bit
0x03 (0x23)
Read/Write
Initial Value
152.
ADPS2
1
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
R/W
BIN
15
15
R
R
R
R
–
7
0
0
7
0
0
7
0
ADC6
ADC8
ADC0
GSEL
R/W
14
14
R
R
R
R
ADPS1
–
6
0
0
6
0
0
6
0
0
0
1
1
ADC5
ADC7
R/W
13
13
R
R
R
R
–
5
0
0
–
5
0
0
5
0
-
REFS2
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
4
0
ADPS0
0
1
0
1
ADC3
ADC5
MUX5
11
11
R
R
R
R
R
–
3
0
0
–
3
0
0
3
0
ADTS2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
R
R
9
1
0
0
9
–
1
0
0
1
0
128
16
32
64
ADTS0
ADC8
ADC0
ADC2
R/W
R
R
R
R
0
0
8
0
0
0
8
–
0
0
0
2588B–AVR–11/06
ADCSRB
ADCH
ADCL
ADCH
ADCL