ATTINY861-15MZ Atmel, ATTINY861-15MZ Datasheet - Page 147

• Manufacturer Part Number: ATTINY861-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6
2588B–AVR–11/06
Changing Channel or Reference Selection
Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 19-7. ADC Timing Diagram, Free Running Conversion
Table 19-1.
The MUX5:0 and REFS2:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
Condition
First conversion
Normal conversions
Auto Triggered conversions
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
ADC Conversion Time
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Conversion
Sample & Hold
(Cycles from Start of Conversion)
Complete
3
One Conversion
Sample &
Hold
11
4
12
5
6
13
13.5
1.5
2
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
9
3
10
Conversion
ATtiny261/461/861
Complete
Sample & Hold
11
4
Conversion Time (Cycles)
12
13
Sign and MSB of Result
13.5
25
13
LSB of Result
Next Conversion
1
Prescaler
Reset
2
147